Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay

Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in the cache's unused sections with minimal impact on performance. Current proposals for resizable caches fundamentally vary in two design aspects: (1) cache organization, where one organization, referred to as selective-ways, varies the cache's set-associativity, while the other, referred to as selectivesets, varies the number of cache sets, and (2) resizing strategy, where one proposal statically sets the cache size prior to an application's execution, while the other allows for dynamic resizing both within and across applications. In this paper, we compare and contrast, for the first time, the proposed design choices for resizable caches, and evaluate the effectiveness of cache resizings in reducing the o...

• Type: Conference
• Year: 2002
• Where: HPCA
• Authors: Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar
• Keywords: Cache Requirement Variability, Cache Size, Computer Architecture, HPCA 2002, Selective-sets-andways Cache Organization