121 search results - page 6 / 25 » Hybrid cache architecture with disparate memory technologies |
ISCA
1993
IEEE
13 years 10 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
CASES
2009
ACM
13 years 10 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
3DIC
2009
IEEE
14 years 1 months ago
2009
IEEE
The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resis...
WIESS
2000
13 years 8 months ago
2000
The HP V-Class server family provides up to 32 processors and 32 GB of memory in a single cabinet. Scalable Computing Architecture technology allows multiple V-Class cabinets to b...