The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...
Dimensional reduction is a simplification technique that eliminates one or more dimensions from a boundary value problem. It results in significant computational savings with mini...
To have a robust and informative image content representation for image categorization, we often need to extract as many as possible visual features at various locations, scales a...
An algorithm and implementation is presented to compute the exact arrangement induced by arbitrary algebraic surfaces on a parametrized ring Dupin cyclide. The family of Dupin cyc...
Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequenti...