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ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 2 months ago
A fast logic simulator using a look up table cascade emulator
— This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascade...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
ACSD
2005
IEEE
71views Hardware» more  ACSD 2005»
14 years 2 months ago
Maximal Causality Analysis
Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algo...
Klaus Schneider, Jens Brandt, Tobias Schüle, ...
EDCC
2005
Springer
14 years 2 months ago
Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs
Abstract. Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSB...
Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jut...
VLSI
2005
Springer
14 years 2 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
VMCAI
2005
Springer
14 years 2 months ago
Information Flow Analysis for Java Bytecode
Abstract. We present a context-sensitive compositional analysis of information flow for full (mono-threaded) Java bytecode. Our idea consists in transforming the Java bytecode int...
Samir Genaim, Fausto Spoto