In recent years, Boolean Satisfiability (SAT) has been shown to hold potential for Unbounded Model Checking (UMC). The success of SAT-based UMC largely relies on (i) the SAT solv...
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Prior work has shown that reduced, ordered, binary decision diagrams (BDDs) can be a powerful tool for program trace analysis and visualization. Unfortunately, it can take hours o...
The problem of finding a collection of solutions to a combinatorial problem that is optimal in terms of an inter-solution objective function exists in many application settings. F...
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits’ primary inputs and outputs must be in pure logic states ...