713 search results - page 116 / 143 » Hybrid transactional memory |
MJ
2008
13 years 8 months ago
2008
This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reco...
VIS
2009
IEEE
14 years 9 months ago
2009
IEEE
Stackless traversal techniques are often used to circumvent memory bottlenecks by avoiding a stack and replacing return traversal with extra computation. This paper addresses wheth...
SC
2009
ACM
14 years 3 months ago
2009
ACM
Memory bandwidth limits the performance of important kernels in many scientific applications. Such applications often use sequences of Basic Linear Algebra Subprograms (BLAS), an...
AINA
2007
IEEE
14 years 3 months ago
2007
IEEE
We know how to build secure systems but for security measures to be truly effective it is necessary to use keys which are far too large for people to commit to memory. The consequ...
HPCA
2007
IEEE
14 years 2 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...