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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 1 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
CSFW
1998
IEEE
14 years 1 months ago
Proving Security Protocols with Model Checkers by Data Independence Techniques
Model checkers such as FDR have been extremely e ective in checking for, and nding, attacks on cryptographic protocols { see, for example 11, 12, 14] and many of the papers in 3]....
A. W. Roscoe
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
14 years 14 days ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
ECOOP
2006
Springer
14 years 12 days ago
A Semantic Analysis of C++ Templates
Templates are a powerful but poorly understood feature of the C++ language. Their syntax resembles the parameterized classes of other languages (e.g., of Java). But because C++ sup...
Jeremy G. Siek, Walid Taha
CGI
2001
IEEE
14 years 12 days ago
Javra: A Simple, Extensible Java Package for VRML
Javra is a Java package for handling VRML scene graphs; it operates either stand-alone or in combination with a VRML browser. The combination of Javra and a VRML browser forms an ...
Huub van de Wetering