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FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
14 years 1 months ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
RSP
2008
IEEE
182views Control Systems» more  RSP 2008»
14 years 1 months ago
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
RSP
2006
IEEE
116views Control Systems» more  RSP 2006»
14 years 1 months ago
Performance Evaluation of an Adaptive FPGA for Network Applications
This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBla...
Christoforos Kachris, Stamatis Vassiliadis
FPGA
2007
ACM
119views FPGA» more  FPGA 2007»
14 years 1 months ago
Synthesis of an application-specific soft multiprocessor system
The application-specific multiprocessor System-on-a-Chip is a promising design alternative because of its high degree of flexibility, short development time, and potentially high ...
Jason Cong, Guoling Han, Wei Jiang
IPPS
2006
IEEE
14 years 1 months ago
An adaptive system-on-chip for network applications
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik...