64-bit floating-point FPGA matrix multiplication

We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algorithm, applicable for an arbitrary matrix size is proposed. The algorithm potentially enables optimum performance by exploiting the data locality and reusability incurred by the general matrix multiplication scheme and considering the limitations of the I/O bandwidth and the local storage volume. We implement a scalable linear array of processing elements (PE) supporting the proposed algorithm in the Xilinx Virtex II Pro technology. Synthesis results confirm a superior performance-area ratio compared to related recent works. Assuming the same FPGA chip, the same amount of local memory, and the same I/O bandwidth, our

• Type: Conference
• Year: 2005
• Where: FPGA
• Authors: Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev
• Keywords: FPGA 2005, Hardware, I/O Bandwidth, Matrix Multiplication, Matrix Multiplication Algorithm