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» IXM2: A Parallel Associative Processor
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IEEEPACT
2009
IEEE
13 years 5 months ago
Region Based Structure Layout Optimization by Selective Data Copying
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
Sandya S. Mannarswamy, Ramaswamy Govindarajan, Ris...
SIGARCH
2008
107views more  SIGARCH 2008»
13 years 7 months ago
Multitasking workload scheduling on flexible core chip multiprocessors
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
Divya Gulati, Changkyu Kim, Simha Sethumadhavan, S...
EUROPAR
1999
Springer
13 years 11 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
ICECCS
1998
IEEE
161views Hardware» more  ICECCS 1998»
13 years 11 months ago
A Method and a Technique to Model and Ensure Timeliness in Safety Critical Real-Time Systems
The main focus of this paper is the problem of ensuring timeliness in safety critical systems. First, we introduce a method and its associated technique to model both real-time ta...
Christophe Aussaguès, Vincent David
GRID
2006
Springer
13 years 7 months ago
Metascheduling Multiple Resource Types using the MMKP
Grid computing involves the transparent sharing of computational resources of many types by users across large geographic distances. The altruistic nature of many current grid reso...
Daniel C. Vanderster, Nikitas J. Dimopoulos, Randa...