305 search results - page 43 / 61 » Impact of Parallel Workloads on NoC Architecture Design |
PDP
2010
IEEE
13 years 12 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
CCGRID
2008
IEEE
14 years 2 months ago
2008
IEEE
Most existing Grid technology has been foremost designed with performance and scalability in mind. When using Grid infrastructure for medical applications, privacy and security co...
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
HPCC
2005
Springer
14 years 1 months ago
2005
Springer
Nowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keep...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...