305 search results - page 43 / 61 » Impact of Parallel Workloads on NoC Architecture Design |
147
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PDP
2010
IEEE
15 years 9 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
144
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CCGRID
2008
IEEE
16 years 3 hour ago
2008
IEEE
Most existing Grid technology has been foremost designed with performance and scalability in mind. When using Grid infrastructure for medical applications, privacy and security co...
159
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ISPASS
2009
IEEE
16 years 10 days ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
159
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HPCC
2005
Springer
15 years 11 months ago
2005
Springer
Nowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keep...
138
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...