119 search results - page 13 / 24 » Impact of Technology Scaling on Digital Subthreshold Circuit... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
As technology scales to 40nm and beyond, intra-die process variability will cause large delay and leakage variations across a chip in addition to expected die-to-die variations. I...