This paper presents figures of merit and error formulae to determine which interconnects require volume discretization in the GHZ range. Most of the previous work focused mainly o...
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
With aggressive technology scaling, integrated circuits suffer from everincreasing wearout effects and their lifetime reliability has become a serious concern for the industry. Fo...
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...