— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
Youssef Serrestou, Vincent Beroulle, Chantal Robac...
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
Abstract-- Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based ...
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis A...
Due to the high cost of modeling, model-based techniques are yet to make their impact in the embedded systems industry, which still persist on maintaining code-oriented legacy sys...
Joel Huselius, Johan Kraft, Hans Hansson, Sasikuma...