801 search results - page 14 / 161 » Implementation and Use of Transactional Memory with Dynamic ... |
POPL
2009
ACM
14 years 8 months ago
2009
ACM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
ISVLSI
2003
IEEE
14 years 25 days ago
2003
IEEE
The behavior of many algorithms is heavily determined by the input data. Furthermore, this often means that multiple and completely different execution paths can be followed, also...
ISCA
2002
IEEE
14 years 14 days ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...