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ICC
2007
IEEE
14 years 3 months ago
Locating Congested Segments on the Internet by Clustering the Delay Performance of Multiple Paths
— A practical method of locating congested segments on the Internet by periodic end-to-end packet delay measurements along multiple paths is presented. This method is a network t...
Atsuo Tachibana, Shigehiro Ano, Toru Hasegawa, Mas...
FPL
2000
Springer
116views Hardware» more  FPL 2000»
14 years 19 days ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...
SIGMOD
2010
ACM
188views Database» more  SIGMOD 2010»
14 years 1 months ago
A demonstration of FlexPref: extensible preference evaluation inside the DBMS engine
This demonstration presents FlexPref, a framework implemented inside the DBMS query processor that enables efficient and extensible preference query processing. FlexPref provides ...
Justin J. Levandoski, Mohamed F. Mokbel, Mohamed E...
ISORC
2007
IEEE
14 years 3 months ago
Evaluating Real-Time Publish/Subscribe Service Integration Approaches in QoS-Enabled Component Middleware
As quality of service (QoS)-enabled component middleware technologies gain widespread acceptance to build distributed real-time and embedded (DRE) systems, it becomes necessary fo...
Gan Deng, Ming Xiong, Aniruddha S. Gokhale, George...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 6 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He