164 search results - page 16 / 33 » Implementation of a SliM Array Processor |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. In this paper,...
ISCAS
2003
IEEE
14 years 20 days ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
CF
2007
ACM
2007
ACM
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
13 years 11 months ago
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
EH
1999
IEEE
13 years 11 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
ICDT
2001
ACM
13 years 12 months ago
2001
ACM
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...