418 search results - page 23 / 84 » Implementation of a Streaming Execution Unit |
JUCS
2007
13 years 9 months ago
2007
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
AICT
2006
IEEE
14 years 1 months ago
2006
IEEE
We present NetTraveler a database middleware system for WANs that is designed to efficiently run queries over sites that are either mobile clients or enterprise servers. NetTravel...
FPL
2006
Springer
14 years 1 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
NOCS
2007
IEEE
14 years 4 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...