Sciweavers

884 search results - page 137 / 177
» Implementation of the MLP Kernel
Sort
View
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 2 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
RTSS
1992
IEEE
14 years 2 months ago
Scheduling Sporadic Tasks with Shared Resources in Hard-Real-Time Systems
The problem of scheduling a set of sporadic tasks that share a set of serially reusable, single unit software resources on a single processor is considered. The correctness condit...
Kevin Jeffay
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 1 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
BTW
2007
Springer
133views Database» more  BTW 2007»
14 years 1 months ago
Pathfinder: XQuery Compila-tion Techniques for Relational Database Targets
: Relational database systems are highly efficient hosts to table-shaped data. It is all the more interesting to see how a careful inspection of both, the XML tree structure as wel...
Jens Teubner
CCS
2007
ACM
14 years 1 months ago
A framework for diversifying windows native APIs to tolerate code injection attacks
We present a framework to prevent code injection attacks in MS Windows using Native APIs in the operating system. By adopting the idea of diversity, this approach is implemented i...
Lynette Qu Nguyen, Tufan Demir, Jeff Rowe, Francis...