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MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 2 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
MICRO
2007
IEEE
94views Hardware» more  MICRO 2007»
14 years 1 months ago
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
Snoopy cache coherence can be implemented in any physical network topology by embedding a logical unidirectional ring in the network. Control messages are forwarded using the ring...
Karin Strauss, Xiaowei Shen, Josep Torrellas
ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
13 years 12 months ago
On the value locality of store instructions
Value locality, a recently discovered program attribute that describes the likelihood of the recurrence of previously-seen program values, has been studied enthusiastically in the...
Kevin M. Lepak, Mikko H. Lipasti
HPCA
1998
IEEE
13 years 11 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...
EUROPAR
2006
Springer
13 years 11 months ago
COPRA - A Communication Processing Architecture for Wireless Sensor Networks
Abstract. Typical sensor nodes are composed of cheap hardware because they have to be affordable in great numbers. This means that memory and communication bandwidth are small, CPU...
Reinhardt Karnapke, Jörg Nolte