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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
SAS
2009
Springer
147views Formal Methods» more  SAS 2009»
14 years 8 months ago
Polymorphic Fractional Capabilities
Abstract. The capability calculus is a framework for statically reasoning about program resources such as deallocatable memory regions. Fractional capabilities, originally proposed...
Hirotoshi Yasuoka, Tachio Terauchi
MSS
2000
IEEE
113views Hardware» more  MSS 2000»
14 years 12 hour ago
Jiro Storage Management
The Jiro™ technology provides an environment intended for the implementation of storage management solutions. A product based on Jiro technology is an implementation based on th...
Bruce K. Haddon, William H. Connor
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
14 years 28 days ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
CORR
2008
Springer
120views Education» more  CORR 2008»
13 years 7 months ago
Network Protection Codes: Providing Self-healing in Autonomic Networks Using Network Coding
Agile recovery from link failures in autonomic communication networks is essential to increase robustness, accessibility, and reliability of data transmission. However, this must b...
Salah A. Aly, Ahmed E. Kamal