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» Implementing LDPC Decoding on Network-on-Chip
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VTC
2008
IEEE
115views Communications» more  VTC 2008»
14 years 2 months ago
Graph-Based Turbo DeCodulation with LDPC Codes
—Turbo DeCodulation is the combination of iterative demodulation and iterative source-channel decoding in a multiple Turbo process. The receiver structures of bit-interleaved cod...
Birgit Schotsch, Laurent Schmalen, Peter Vary, Tho...
ISCAS
2006
IEEE
99views Hardware» more  ISCAS 2006»
14 years 1 months ago
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor
— By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error ra...
Hao Zhong, Tong Zhang, Erich F. Haratsch
CORR
2010
Springer
109views Education» more  CORR 2010»
13 years 7 months ago
Dirty Paper Coding using Sign-bit Shaping and LDPC Codes
Dirty paper coding (DPC) refers to methods for pre-subtraction of known interference at the transmitter of a multiuser communication system. There are numerous applications for DPC...
G. Shilpa, Andrew Thangaraj, Srikrishna Bhashyam
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
ICC
2008
IEEE
141views Communications» more  ICC 2008»
14 years 2 months ago
Multilevel Structured Low-Density Parity-Check Codes
— Low-Density Parity-Check (LDPC) codes are typically characterized by a relatively high-complexity description, since a considerable amount of memory is required in order to sto...
Nicholas Bonello, Sheng Chen, Lajos Hanzo