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» Implementing Optimizations at Decode Time
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INFOCOM
2003
IEEE
14 years 1 months ago
Adaptive Data Structures for IP Lookups
— The problem of efficient data structures for IP lookups has been well studied in literature. Techniques such as LC tries and Extensible Hashing are commonly used. In this pape...
Ioannis Ioannidis, Ananth Grama, Mikhail J. Atalla...
CF
2010
ACM
14 years 1 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
PLDI
1994
ACM
14 years 21 hour ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
CF
2007
ACM
13 years 12 months ago
Parallel genomic sequence-search on a massively parallel system
In the life sciences, genomic databases for sequence search have been growing exponentially in size. As a result, faster sequencesearch algorithms to search these databases contin...
Oystein Thorsen, Brian E. Smith, Carlos P. Sosa, K...
CDES
2006
158views Hardware» more  CDES 2006»
13 years 9 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia