Sciweavers

5562 search results - page 967 / 1113
» Implementing Parallel Cell-DEVS
Sort
View
IEEEPACT
2003
IEEE
15 years 8 months ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
IEEEPACT
2003
IEEE
15 years 8 months ago
Reactive Multi-Word Synchronization for Multiprocessors
Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hard...
Phuong Hoai Ha, Philippas Tsigas
ISPASS
2003
IEEE
15 years 8 months ago
Complete instrumentation requirements for performance analysis of Web based technologies
In this paper we present the eDragon environment, a research platform created to perform complete performance analysis of new Web-based technologies. eDragon enables the understan...
David Carrera, Jordi Guitart, Jordi Torres, Eduard...
112
Voted
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
15 years 8 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
157
Voted
SI3D
2003
ACM
15 years 7 months ago
Interactive visibility culling in complex environments using occlusion-switches
: We present occlusion-switches for interactive visibility culling in complex 3D environments. An occlusionswitch consists of two GPUs (graphics processing units) and each GPU is u...
Naga K. Govindaraju, Avneesh Sud, Sung-Eui Yoon, D...