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» Implementing a STARI chip
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ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 4 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 7 months ago
Implementing LDPC Decoding on Network-on-Chip
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...
NOCS
2008
IEEE
14 years 1 months ago
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, ...
ASPDAC
2009
ACM
105views Hardware» more  ASPDAC 2009»
14 years 16 hour ago
Design and chip implementation of the ubiquitous processor HCgorilla
Masa-Aki Fukase, Kazunori Noda, Atsuko Yokoyama, T...