857 search results - page 145 / 172 » Implementing a STARI chip |
APNOMS
2006
Springer
14 years 5 days ago
2006
Springer
This paper intends to introduce the development of a terminal agent for QoS measurement that is suitable for an NGN environment, and to summarize the results of its performance tes...
DSD
2004
IEEE
14 years 5 days ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
DSD
2006
IEEE
14 years 3 days ago
2006
IEEE
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
ANSS
2001
IEEE
14 years 3 days ago
2001
IEEE
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...
ATS
2001
IEEE
14 years 3 days ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...