857 search results - page 147 / 172 » Implementing a STARI chip |
CSREAESA
2008
13 years 10 months ago
2008
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
ERSA
2008
13 years 10 months ago
2008
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...
ERSA
2006
13 years 9 months ago
2006
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
VMV
2001
13 years 9 months ago
2001
In this paper we demonstrate the benefits of the most current nVidia graphics chip set for realistic simulation and rendering of dynamic water surfaces in real-time. In particular...
WSCG
2004
13 years 9 months ago
2004
3D design software has since long employed graphics chips for low-quality real-time previewing. But their dramatically increased computing power now paves the way to accelerate th...