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» Implementing a STARI chip
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FDL
2004
IEEE
13 years 11 months ago
A Functional Programming Framework of Heterogeneous Model of Computation for System Design
System-on-Chip (SOC) and other complex distributed hardware/software systems contain heterogeneous components such as DSPs, micro-controllers, application specific logic etc., whi...
Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shu...
EUC
2006
Springer
13 years 11 months ago
Write Back Routine for JFFS2 Efficient I/O
Abstract. When flash memory is used as a storage in embedded systems, block level translation layer is required between conventional filesystem and flash memory chips due to its ph...
Seung Ho Lim, Sung Hoon Baek, Joo Young Hwang, Kyu...
ASPLOS
2008
ACM
13 years 9 months ago
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
Extracting high-performance from the emerging Chip Multiprocessors (CMPs) requires that the application be divided into multiple threads. Each thread executes on a separate core t...
M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Pa...
BMCBI
2007
151views more  BMCBI 2007»
13 years 7 months ago
The Genopolis Microarray Database
Background: Gene expression databases are key resources for microarray data management and analysis and the importance of a proper annotation of their content is well understood. ...
Andrea Splendiani, Marco Brandizi, Gael Even, Otta...
DAC
2009
ACM
14 years 8 months ago
Handling complexities in modern large-scale mixed-size placement
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...
Jackey Z. Yan, Natarajan Viswanathan, Chris Chu