Sciweavers

857 search results - page 20 / 172
» Implementing a STARI chip
Sort
View
ISCAS
2003
IEEE
107views Hardware» more  ISCAS 2003»
14 years 19 days ago
On chip Gaussian processing for high resolution CMOS image sensors
Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and can be mathematically represented as the Laplacian of Gaussian (LO...
Sri Vinayagamoorthy, Richard Hornsey
PPL
2008
117views more  PPL 2008»
13 years 7 months ago
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips
This discussion paper explores the problems of operating systems support when implementing concurrency controls at the level of the instruction set in processors designed for mult...
Chris R. Jesshope
JUCS
2010
143views more  JUCS 2010»
13 years 5 months ago
Design of Arbiters and Allocators Based on Multi-Terminal BDDs
: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways...
Václav Dvorák, Petr Mikusek
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
14 years 1 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
FCCM
2005
IEEE
96views VLSI» more  FCCM 2005»
14 years 29 days ago
FPGA-Based CDMA Switch for Networks-on-Chip
This paper presents timing and area results for an FPGA implementation of a CDMA-based switch for networkson-chip. The design was mapped onto the Xilinx Virtex4 XC4VLX200 device u...
Daewook Kim, Manho Kim, Gerald E. Sobelman