857 search results - page 44 / 172 » Implementing a STARI chip |
ISVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
ITCC
2005
IEEE
14 years 4 months ago
2005
IEEE
The interconnection network plays an important role in the performance and energy consumption of a Networkon-Chip (NoC) system. In this paper, we propose a RDT(2,2,1)/α-based int...
SBCCI
2003
ACM
14 years 4 months ago
2003
ACM
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
GLVLSI
1999
IEEE
14 years 3 months ago
1999
IEEE
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...