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» Implementing the scale vector-thread processor
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ISLPED
2006
ACM
145views Hardware» more  ISLPED 2006»
14 years 1 months ago
An optimal analytical solution for processor speed control with thermal constraints
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
ICANN
2005
Springer
14 years 1 months ago
A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor
Abstract. A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project,...
Martin J. Pearson, Ian Gilhespy, Kevin N. Gurney, ...
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
14 years 24 days ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson
RSP
2007
IEEE
158views Control Systems» more  RSP 2007»
14 years 1 months ago
SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems
A widely used approach to avoid network intrusion is SNORT, an open source Network Intrusion Detection System (NIDS). This work describes SPP-NIDS, a architecture for intrusion de...
Luis Carlos Caruso, Guilherme Guindani, Hugo Schmi...
TVLSI
2008
85views more  TVLSI 2008»
13 years 7 months ago
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Chip-Multi-Processors (CMP) utilize multiple energy-efficient Processing Elements (PEs) to deliver high performance while maintaining an efficient ratio of performance to energy-c...
A. Elyada, Ran Ginosar, Uri Weiser