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» Implementing the scale vector-thread processor
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IPPS
2007
IEEE
14 years 1 months ago
File Creation Strategies in a Distributed Metadata File System
As computing breaches petascale limits both in processor performance and storage capacity, the only way that current and future gains in performance can be achieved is by increasi...
Ananth Devulapalli, Pete Wyckoff
ICCAD
2009
IEEE
171views Hardware» more  ICCAD 2009»
13 years 5 months ago
A hybrid local-global approach for multi-core thermal management
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...
Ramkumar Jayaseelan, Tulika Mitra
VEE
2010
ACM
327views Virtualization» more  VEE 2010»
14 years 2 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
14 years 1 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
CODES
2008
IEEE
13 years 9 months ago
Power reduction via macroblock prioritization for power aware H.264 video applications
As the importance of multimedia applications in hand-held devices increases, the computational strain and corresponding demand for energy in such devices continues to grow. Portab...
Michael A. Baker, Viswesh Parameswaran, Karam S. C...