244 search results - page 36 / 49 » Implementing the scale vector-thread processor |
SSDBM
2010
IEEE
14 years 19 days ago
2010
IEEE
Science is becoming data-intensive, requiring new software architectures that can exploit resources at all scales: local GPUs for interactive visualization, server-side multi-core ...
DATE
2002
IEEE
14 years 15 days ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
HOTI
2002
IEEE
14 years 15 days ago
2002
IEEE
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
WACV
2002
IEEE
14 years 13 days ago
2002
IEEE
This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specif...
HICSS
1999
IEEE
13 years 12 months ago
1999
IEEE
The main objective of the IBM Grand Central Station (GCS) is to gather information of virtually any type of formats (text, data, image, graphics, audio, video) from the cyberspace...