Low Power Error Resilient Encoding for On-Chip Data Buses

As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced effects, etc. Transient delay and logic faults are likely to reduce the reliability of data transfers across datapath bus lines. This paper investigates how to deal with these errors in an energy efficient way. We could opt for error correction, which exhibits larger decoding overhead, or for the retransmission of the incorrectly received data word. Provided the timing penalty associated with this latter technique can be tolerated, we show that retransmission strategies are more effective than correction ones from an energy viewpoint, both for the larger detection capability and for the minor decoding complexity. The analysis was performed by implementing several variants of a Hamming code in the VHDL model of a processor based on the Sparc V8 architecture, and exploiting the characteristics of AMBA bus slave ...

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Davide Bertozzi, Luca Benini, Giovanni De Micheli
• Keywords: Datapath Bus Lines, DATE 2002, Hardware, Larger Decoding Overhead, On-chip Interconnects