28 search results - page 5 / 6 » Implicates and Reduction Techniques for Temporal Logics |
ISQED
2011
IEEE
12 years 11 months ago
2011
IEEE
With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the microprocesso...
TCAD
2002
13 years 7 months ago
2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
This article introduces a fully automated verification technique that permits to analyze real-time systems described using a continuous notion of time and a mixture of operational...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
FMCAD
1998
Springer
13 years 11 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...