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ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
NOSSDAV
2005
Springer
14 years 1 months ago
2005
Springer
We propose an efficient placement algorithm and per-disk prefetching method to effectively support interactive operations in the media server. Our placement policy is incorporate...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...