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PLDI
1995
ACM
13 years 11 months ago
Tile Size Selection Using Cache Organization and Data Layout
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for ch...
Stephanie Coleman, Kathryn S. McKinley
CAIP
2009
Springer
140views Image Analysis» more  CAIP 2009»
13 years 10 months ago
Hierarchical Decomposition of Handwritten Manuscripts Layouts
Abstract. In this paper we propose a new approach to improve electronic editions of literary corpus, providing an efficient estimation of manuscripts pages structure. In any handwr...
Vincent Malleron, Véronique Eglin, Hubert E...
WSC
1998
13 years 8 months ago
The Use of Simulation in Facility Layout Design: A Practical Consulting Experience
This paper presents a practical undertaking to solve an industry-specific problem of facility expansion through relocation of an existing production facility to a proposed new fac...
Emmanuel S. Eneyo, Gertrude P. Pannirselvam
CODES
2001
IEEE
13 years 11 months ago
Compiler-directed selection of dynamic memory layouts
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
Mahmut T. Kandemir, Ismail Kadayif
IEEEPACT
2009
IEEE
13 years 5 months ago
Region Based Structure Layout Optimization by Selective Data Copying
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
Sandya S. Mannarswamy, Ramaswamy Govindarajan, Ris...