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PLDI
1999
ACM
13 years 11 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
SPATIALCOGNITION
2000
Springer
13 years 11 months ago
Interactive Layout Generation with a Diagrammatic Constraint Language
The paper analyzes a diagrammatic reasoning problem that consists in finding a graphical layout which simultaneously satisfies a set of constraints expressed in a formal language a...
Christoph Schlieder, Cornelius Hagen
TCAD
2002
135views more  TCAD 2002»
13 years 7 months ago
Area fill synthesis for uniform layout density
Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local character...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
VISUALIZATION
1992
IEEE
13 years 11 months ago
Improving the Visualization of Hierarchies with Treemaps: Design Issues and Experimentation
Controlled experiments with novice treemap users and real data highlight the strengths of treemaps and provide direction for improvement. Issues discussed include experimental res...
David Turo, B. Johnson
SOSP
2005
ACM
14 years 4 months ago
FS2: dynamic data replication in free disk space for improving disk performance and energy consumption
Disk performance is increasingly limited by its head positioning latencies, i.e., seek time and rotational delay. To reduce the head positioning latencies, we propose a novel tech...
Hai Huang, Wanda Hung, Kang G. Shin