Area fill synthesis for uniform layout density

Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local characteristics of the layout. To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting "area fill" geometries into the layout. In this paper, we make the following contributions. First, we define the flat, hierarchical and multiple-layer filling problems, along with a unified density model description. Secondly, for the flat filling problem, we summarize current linear programming approaches with two different objectives, i.e., the Min-Var and Min-Fill objectives. We then propose several new Monte-Carlo based filling methods with fast dynamic data structures. Third, we give practical iterated methods for layout density control for CMP uniformity based on linear programming, Monte-Carlo and greedy algorithms. Fourt...

• Type: Journal
• Year: 2002
• Where: TCAD
• Authors: Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
• Keywords: Filling Problem, Layout Density Control, Multiple-layer Filling Problem, TCAD 2002