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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 4 months ago
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...
ISPD
2006
ACM
156views Hardware» more  ISPD 2006»
14 years 1 months ago
Improved method of cell placement with symmetry constraints for analog IC layout design
Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyosh...
CCCG
2007
13 years 8 months ago
Improved Layouts of the Multigrid Network
In a previous paper, Calamoneri and Massini studied the problem of drawing the multigrid network in “a grid of minimum area”. In this paper we show that we can draw the multig...
Shabnam Aziza, Therese C. Biedl
ECEASST
2008
80views more  ECEASST 2008»
13 years 7 months ago
Positioning Map: a Visual Technique to Improve the Layout of Diagram Contextual Information
Nicolas Genon, Raimundas Matulevicius, Vincent Eng...