376 search results - page 4 / 76 » Improved Design Debugging Using Maximum Satisfiability |
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
ICCS
2005
Springer
14 years 2 days ago
2005
Springer
In this paper we address two optimization problems arising in the design of genomic assays based on universal tag arrays. First, we address the universal array tag set design probl...
TIT
2011
13 years 1 months ago
2011
For integer r satisfying 0 ≤ r ≤ p − 2, a sequence family Ωr of polyphase sequences of prime period p, size (p − 2)pr , and maximum correlation at most 2 + (r + 1) √ p...
CODES
2008
IEEE
13 years 8 months ago
2008
IEEE
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We...