455 search results - page 17 / 91 » Improved Force-Directed Layouts |
ASPDAC
2005
ACM
14 years 3 months ago
2005
ACM
The sustained miniaturization of VLSI feature size presents great challenges to sub-wavelength photolithography and requests usage of many Resolution Enhancement Techniques (RET)....
ASPDAC
1999
ACM
14 years 2 months ago
1999
ACM
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
CACM
2004
13 years 9 months ago
2004
We present and explore a simple idea for improving document layout on arbitrary devices of different resolutions and size. The key idea is to allow manifold representations of con...
EURODAC
1995
IEEE
14 years 1 months ago
1995
IEEE
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...
ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...