2201 search results - page 136 / 441 » Improvement of ASIC Design Processes |
TSP
2008
13 years 10 months ago
2008
Abstract--In this paper, we develop an adaptive waveform design method for target tracking under a framework of sequential Bayesian inference. We employ polarization diversity to i...
DSN
2011
IEEE
12 years 10 months ago
2011
IEEE
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...
DAC
2008
ACM
14 years 11 months ago
2008
ACM
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...
DAC
2004
ACM
14 years 11 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
WWW
2009
ACM
14 years 10 months ago
2009
ACM
Loose coupling is often quoted as a desirable property of systems architectures. One of the main goals of building systems using Web technologies is to achieve loose coupling. How...