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» Improvement of ASIC Design Processes
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DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 9 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
114
Voted
HOTI
2005
IEEE
15 years 9 months ago
Design and Implementation of a Content-Aware Switch Using a Network Processor
Cluster based server architectures have been widely used as a solution to overloading in web servers because of their cost effectiveness, scalability and reliability. A content aw...
Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. ...
103
Voted
IRI
2005
IEEE
15 years 9 months ago
Knowledge representation for product design using Techspecs Concept Ontology
Sharing and reusing product design information can help reduce cost and time when developing new products and facilitate good product family design. An appropriate representation ...
Seung Ki Moon, Soundar R. T. Kumara, Timothy W. Si...
131
Voted
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
15 years 8 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
SIGMETRICS
2010
ACM
178views Hardware» more  SIGMETRICS 2010»
15 years 8 months ago
Optimality, fairness, and robustness in speed scaling designs
System design must strike a balance between energy and performance by carefully selecting the speed at which the system will run. In this work, we examine fundamental tradeoffs i...
Lachlan L. H. Andrew, Minghong Lin, Adam Wierman