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» Improvement of ASIC Design Processes
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AHS
2006
IEEE
137views Hardware» more  AHS 2006»
14 years 1 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
APCCAS
2006
IEEE
245views Hardware» more  APCCAS 2006»
14 years 1 months ago
Digital Audio Broadcasting System Modeling and Hardware Implementation
— DAB is a growing communication technology for digital audio broadcasting and demands higher concentration on flexible and cost optimum implementations for use in new mobile ele...
Nariman Moezzi Madani, Hamed Holisaz, Seid Mehdi F...
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 11 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
IJPP
2006
145views more  IJPP 2006»
13 years 7 months ago
Deterministic Parallel Processing
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
Gajinder Panesar, Daniel Towner, Andrew Duller, Al...
DMDW
2003
134views Management» more  DMDW 2003»
13 years 8 months ago
Using Design Guidelines to Improve Data Warehouse Logical Design
Data Warehouse-(DW) logical design often start with a conceptual schema and then generates relational structures. Applying this approach implies to cope with two main aspects: (i) ...
Verónika Peralta, Raul Ruggia