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» Improvement of ASIC Design Processes
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131
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DAC
2007
ACM
16 years 4 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
99
Voted
DAC
2009
ACM
16 years 4 months ago
Mode grouping for more effective generalized scheduling of dynamic dataflow applications
For a number of years, dataflow concepts have provided designers of digital signal processing systems with environments capable of expressing high-level software architectures as ...
William Plishker, Nimish Sane, Shuvra S. Bhattacha...
125
Voted
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
16 years 17 days ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
131
Voted
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 10 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
121
Voted
DSRT
2008
IEEE
15 years 10 months ago
Observability Checking to Enhance Diagnosis of Real Time Electronic Systems
This paper describes a new property checking approach in order to enhance the diagnosis ability of an electronic embedded system, included in an automotive application. We conside...
Manel Khlif, Mohamed Shawky