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» Improvement of ASIC Design Processes
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245
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AMT
2001
Springer
191views Multimedia» more  AMT 2001»
15 years 8 months ago
An Authoring Tool for Building Adaptive Learning Guidance Systems on the Web
In the field of guided learning on the Internet we present, in this paper, an interactive tool for designing intelligent tutoring systems on the web. Our tool makes easier the crea...
José Antonio Macías Iglesias, Pablo ...
99
Voted
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
15 years 8 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
FPL
1999
Springer
103views Hardware» more  FPL 1999»
15 years 8 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
109
Voted
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
15 years 7 months ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken
ATS
2004
IEEE
109views Hardware» more  ATS 2004»
15 years 7 months ago
Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterj...