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» Improvement of ASIC Design Processes
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ICIP
2001
IEEE
16 years 5 months ago
Compression and transmission of depth maps for image-based rendering
We consider applications using depth-based Imagebased rendering (IBR), where the synthesis of arbitrary views occur at a remote location, necessitating the compression and transmi...
Ravi Krishnamurthy, Bing-Bing Chai, Hai Tao, Srira...
ICASSP
2009
IEEE
15 years 11 months ago
Revisiting graphemes with increasing amounts of data
Letter units, or graphemes, have been reported in the literature as a surprisingly effective substitute to the more traditional phoneme units, at least in languages that enjoy a s...
Yun-Hsuan Sung, Thad Hughes, Françoise Beau...
SASP
2009
IEEE
170views Hardware» more  SASP 2009»
15 years 10 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
ICIP
2007
IEEE
15 years 10 months ago
Rate-Distortion Analysis and Bit Allocation Strategy for Motion Estimation at the Decoder using Maximum Likelihood Technique in
Numerous approaches for distributed video coding have been recently proposed. One of main motivations for these techniques is the possibility of achieving complexity tradeoffs bet...
Ivy H. Tseng, Antonio Ortega
CHES
2007
Springer
126views Cryptology» more  CHES 2007»
15 years 10 months ago
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
Daisuke Suzuki