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» Improvement of ASIC Design Processes
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ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
14 years 1 months ago
A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback
Abstract—This paper presents the design of a two-stage pseudodifferential operational transconductance amplifier (OTA). The circuit was designed in a standard 0.18 µm, 0.5 V VT ...
Michael Trakimas, Sameer R. Sonkusale
IPPS
2006
IEEE
14 years 1 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
SIGSOFT
2001
ACM
14 years 8 months ago
An empirical methodology for introducing software processes
There is a growing interest in empirical study in software engineering, both for validating mature technologies and for guiding improvements of less-mature technologies. This pape...
Forrest Shull, Jeffrey Carver, Guilherme Travassos
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 11 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie