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» Improvement of ASIC Design Processes
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FPL
2006
Springer
137views Hardware» more  FPL 2006»
14 years 14 days ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
SNPD
2003
13 years 10 months ago
Integration of Simulation Based Performance Assessment in a Software Development Process
From the early design phase through the implementation performance assessment of software has been subject to a great variety of approaches in the past. Performance modeling artif...
Michael N. Barth
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 3 months ago
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
TCAD
2008
100views more  TCAD 2008»
13 years 8 months ago
Robust Clock Tree Routing in the Presence of Process Variations
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
CIKM
2005
Springer
14 years 2 months ago
Localized routing trees for query processing in sensor networks
In this paper, we propose a novel energy-efficient approach, a localized routing tree (LRT) coupled with a route redirection (RR) strategy, to support various types of queries. LR...
Jie Lian, Lei Chen 0002, Kshirasagar Naik, M. Tame...